Reso Signal Output Timing - Renesas H8S Family Hardware Manual

RESO Signal Output Timing

12.4.3
When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the
RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time,
the low level signal is output from the RESO pin. The timing is shown in figure 12.5.
φ
TCNT
Overflow signal
(internal signal)
OVF
RESO signal
Internal reset
signal
This LSI has retain state pins, which are only initialized by a system reset. The outputs on these
pins are retained even when an internal reset is generated by the overflow signal of the WDT. For
more information, see section 8, I/O Ports.
H'FF
Figure 12.5 Output Timing of RESO signal
Section 12 Watchdog Timer (WDT)
H'00
132 states
518 states
Rev. 1.00 Mar. 12, 2008 Page 423 of 1178
REJ09B0403-0100