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Section 19 LPC Interface (LPC)
Slave
Bit that indicates slave is ready for write transfer.
Issues when slave is ready for the next write transfer.
Slave confirms that control code is written to SMICCSR
by host.
The CTLWI bit in SMICIR0 is set.
Slave waits for the BUSY bit in SMICFLG is set.
Slave confirms that valid data is written to SMICDTR
by host.
The HDTWI bit in SMICIR0 is set.
Slave confirms the rising edge of the BUSY bit in SMICFLG.
The BUSYI bit in SMICIR0 is set.
Slave clears the TX_DATA_RDY bit in SMICFLG.
Slave reads the control code in SMICCSR.
Slave reads transfer data in SMICDTR according to
Write control code.
Slave writes the status code to SMICCSR to notify
the processing completion status.
Slave clears the BUSY bit in SMICFLG to indicate
transfer completion.
Slave confirms that status code is read from SMICCSR
by host.
The STARI bit in SMICIR0 is set.
Rev. 1.00 Mar. 12, 2008 Page 736 of 1178
REJ09B0403-0100
Wait for BUSY = 0
Wait for
TX_DATA_RDY = 1
A
Write control code
Generate slave
interrupt
Write transfer data
Generate slave
interrupt
BUSY = 1
Generate slave
interrupt
TX_DATA_RDY = 0
Read control code
Read transfer data
Write status code
BUSY = 0
Generate host
interrupt
Abnormal
Read status code
A
Normal
Generate slave
interrupt
Figure 19.4 SMIC Write Transfer Flow
Host
Host confirms the BUSY bit in SMICFLG.
The bit indicates slave (this LSI) is ready for receiving a new control code.
When BUSY = 1, access from host is disabled.
Host confirms the TX_DATA_RDY bit in SMICFLG.
The confirmation is unnecessary when Write Start control is issued.
Host writes the Write control code in SMICCSR.
Host writes transfer data in SMICDTR.
Host sets the BUSY bit in SMICFLG.
Host confirms the falling edge of the BUSY bit in SMICFLG.
An interrupt is generated.
Host confirms the status code in SMICCSR.
In the case of normal completion, the status code is reflected to the next step.
In the case of abnormal completion, the status code is READY and an error
is kept.
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