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Start condition generation
SCL
(Pin waveform)
SCL
(master output)
SCL
(slave output)
SDA
(master output)
SDA
(slave output)
IRIC
ICDRF
ICDRS
ICDRR
User processing
[2] ICDR read
Figure 18.18 Slave Receive Mode Operation Timing Example (1) (MLS = 0, HNDS= 1)
[7] SCL is fixed low until ICDR is read
SCL
8
(master output)
SCL
(slave output)
SDA
Bit 0
(master output)
Data (n-1)
SDA
(slave output)
IRIC
ICDRF
Data (n-1)
ICDRS
Data (n-2)
ICDRR
User processing
[8] IRIC clear
[9] Set ACKB=1
Figure 18.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1)
1
2
3
1
2
3
Bit 7
Bit 6
Bit 5
Slave address
Undefined value
9
1
2
3
Bit 7
Bit 6
Bit 5
[6]
Data (n)
A
Data (n-1)
[10] ICDR read (Data (n-1))
[7] SCL is fixed low until ICDR is read
4
5
6
7
8
4
5
6
7
8
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
[8] IRIC clear
[7] SCL is fixed low until ICDR is read
4
5
6
7
8
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
[8] IRIC clear
Rev. 1.00 Mar. 12, 2008 Page 635 of 1178
2
Section 18 I
C Bus Interface (IIC)
9
1
9
1
Bit 7
Data 1
[6]
A
Interrupt
request
occurrence
Address
+R/W
Address
+R/W
[10] ICDR read (dummy read)
Stop condition generation
9
[6]
[11]
A
Data (n)
Data (n)
[10] ICDR read
[12] IRIC clear
(Data (n))
REJ09B0403-0100
2
2
Bit 6
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