Interrupt Control Mode 0 - Renesas H8S Family Hardware Manual

Operations and Control Signal Functions in Each Interrupt Control Mode

Control Mode

Interrupt operation control performed

Used as an interrupt mask bit

Sets priority

Interrupt Control Mode 0

In interrupt control mode 0, interrupts other than NMI are masked by ICR and the I bit of the CCR

in the CPU. Figure 5.4 shows a flowchart of the interrupt acceptance operation.

1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an

interrupt request is sent to the interrupt controller.

2. According to the interrupt control level specified in ICR, the interrupt controller accepts an

interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request

with interrupt control level 0 (no priority). If several interrupt requests are issued, an interrupt

request with the highest priority is accepted according to the priority order, an interrupt

handling is requested to the CPU, and other interrupt requests are held pending.

3. If the I bit in CCR is set to 1, only NMI and address break interrupt requests are accepted by

the interrupt controller, and other interrupt requests are held pending. If the I bit is cleared to 0,

any interrupt request is accepted. KIN, WUE, and EVENTI interrupts are enabled or disabled

by the I bit.

4. When the CPU accepts an interrupt request, it starts interrupt exception handling after

execution of the current instruction has been completed.

5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on

the stack shows the address of the first instruction to be executed after returning from the

interrupt handling routine.

6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break

Interrupt Acceptance Control

3-Level Control

Rev. 1.00 Mar. 12, 2008 Page 93 of 1178

Section 5 Interrupt Controller

Default Priority

Determination

REJ09B0403-0100