Scif Control Register (Scifcr) - Renesas H8S Family Hardware Manual

Section 15 Serial Communication Interface with FIFO (SCIF)

15.3.14 SCIF Control Register (SCIFCR)

SCIFCR controls SCIF operations, and is accessible only from the CPU.
Bit Bit Name
7 SCIFOE1
6 SCIFOE0

5
4 OUT2LOOP
3 CKSEL1
2 CKSEL0
1 SCIFRST
0 REGRST
Rev. 1.00 Mar. 12, 2008 Page 524 of 1178
REJ09B0403-0100
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
These bits enable or disable PORT output of the
SCIF. The PORT function differs according to the
combination with the SCIF bit in HICR5 of the LPC.
For details, see table 15.4.
Reserved
Do not change the initial value.
Enables or disables interrupts during a loopback
test.
0: Interrupt enabled
1: Interrupt disabled
These bits select the clock (SCLK) to be input to the
baud rate generator.
00: LCLK divided by 18
01: System clock divided by 11
10: Reserved for LCLK (not selectable)
11: Reserved for system clock (not selectable)
Resets the baud rate generator, FRSR, and FTSR.
0: Normal operation
1: Reset
Resets registers (except SCIFCR) accessible from
the H8S CPU or LPC interface.
0: Normal operation
1: Reset