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2
Section 18 I
C Bus Interface (IIC)
MST
TRS
BBSY
ESTP
0
0
1
0
0
0
1
0
0
0
1
0
0
0↓
1↑/0
*
[Legend]
0: 0-state retained
1: 1-state retained
↓
0
: Cleared to 0
1
Notes: 1. Set to 1 when 1 is received as a R/W bit following an address.
2. Set to 1 when the AASX bit is set to 1.
3. When ESTP=1, STOP is 0, or when STOP=1, ESTP is 0.
Rev. 1.00 Mar. 12, 2008 Page 606 of 1178
REJ09B0403-0100
STOP
IRTR
AASX
0
0
0
1↑/0
2
*
0/1↑
3
3
*
: Previous state retained
↑
: Set to 1
AL
AAS
ADZ
ACKB
0↓
0↓
0↓
0
0
0
State
ICDRF
ICDRE
1
Reception
end with
ICDRF=1
0↓
ICDR read
with the
above state
1↑
Automatic
data transfer
from ICDRS
to ICDRR
with the
above state
0↓
Stop
condition
detected
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