Second Slave Address Register (Sarx) - Renesas H8S Family Hardware Manual

18.3.3

Second Slave Address Register (SARX)

SARX sets the second slave address and selects the communication format. In slave mode,
transmit/receive operations by the DTC are possible when the received address matches the
second slave address. When the LSI is in slave mode with the I
bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after
a start condition, the LSI operates as the slave device specified by the master device. SARX can be
accessed only when the ICE bit in ICCR is cleared to 0.
Bit Bit Name
7 SVAX6
6 SVAX5
5 SVAX4
4 SVAX3
3 SVAX2
2 SVAX1
1 SVAX0
0 FSX
Initial
Value
R/W Description
All 0 R/W Second Slave Addresses 6 to 0
Set the second slave address.
1 R/W Format Select X
Selects the communication format together with the FS bit
in SAR. Refer to table 18.2.
2
Section 18 I C Bus Interface (IIC)
2
C bus format selected, if the FSX
Rev. 1.00 Mar. 12, 2008 Page 591 of 1178
REJ09B0403-0100