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Figure 10.11 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Used) ..................................................... 388
Section 11 8-Bit Timer (TMR)
Figure 11.1 Block Diagram of 8-Bit Timer (TMR_0 and TMR_1)............................................ 392
Figure 11.2 Block Diagram of 8-Bit Timer (TMR_Y and TMR_X).......................................... 393
Figure 11.3 Count Timing for Internal Clock Input ................................................................... 404
Figure 11.4 Timing of CMF Setting at Compare-Match ............................................................ 404
Figure 11.5 Timing of Counter Clear by Compare-Match ......................................................... 405
Figure 11.6 Timing of OVF Flag Setting ................................................................................... 405
Figure 11.7 Conflict between TCNT Write and Counter Clear .................................................. 408
Figure 11.8 Conflict between TCNT Write and Increment ........................................................ 409
Figure 11.9 Conflict between TCOR Write and Compare-Match .............................................. 410
Section 12 Watchdog Timer (WDT)
Figure 12.1 Block Diagram of WDT .......................................................................................... 414
Figure 12.2 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 421
Figure 12.3 Interval Timer Mode Operation............................................................................... 422
Figure 12.4 OVF Flag Set Timing .............................................................................................. 422
Figure 12.5 Output Timing of RESO signal ............................................................................... 423
Figure 12.6 Writing to TCNT and TCSR (WDT_0)................................................................... 425
Figure 12.7 Conflict between TCNT Write and Increment ........................................................ 426
Figure 12.8 Sample Circuit for Resetting the System by the RESO Signal................................ 427
Section 13 Serial Communication Interface (SCI)
Figure 13.1 Block Diagram of SCI_1 and SCI_3 ....................................................................... 431
Figure 13.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits).................................................. 449
Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 451
Figure 13.4 Relation between Output Clock and Transmit Data Phase
(Asynchronous Mode)............................................................................................. 452
Figure 13.5 Sample SCI Initialization Flowchart ....................................................................... 453
Figure 13.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 454
Figure 13.7 Sample Serial Transmission Flowchart ................................................................... 455
Figure 13.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 456
Figure 13.9 Sample Serial Reception Flowchart (1)................................................................... 458
Figure 13.9 Sample Serial Reception Flowchart (2)................................................................... 459
Figure 13.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)............................................ 461
Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 462
Rev. 1.00 Mar. 12, 2008 Page xxxii of xIviii
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