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10.3
Operation Timing
10.3.1
FRC Increment Timing
Figure 10.2 shows the FRC increment timing with an internal clock source.
φ
Internal clock
FRC input
clock
FRC
Figure 10.2 Increment Timing with Internal Clock Source
10.3.2
Output Compare Output Timing
A compare-match signal occurs at the last state when the FRC and OCR values match (at the
timing when the FRC updates the counter value). When a compare-match signal occurs, the level
selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB). Figure
10.3 shows the timing of this operation for compare-match A.
φ
FRC
OCRA
N – 1
N
N + 1
N
Figure 10.3 Timing of Output Compare A Output
Section 10 16-Bit Free-Running Timer (FRT)
N
N
Rev. 1.00 Mar. 12, 2008 Page 381 of 1178
N + 1
N + 1
N
REJ09B0403-0100
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