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Section 19 LPC Interface (LPC)
Bit
Bit Name Initial Value Slave Host Description
1
IRQ9E2
0
0
IRQ6E2
0
Rev. 1.00 Mar. 12, 2008 Page 706 of 1178
REJ09B0403-0100
R/W
R/W
Host IRQ9 Interrupt Enable 2
Enables or disables an HIRQ9 interrupt request
when OBF2 is set by an oDR2 write.
0: HIRQ9 interrupt request by OBF2 and IRQE9E2
is disabled
[Clearing conditions]
•
Writing 0 to IRQ9E2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
HIRQ9 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR2 = 1]
HIRQ9 interrupt is requested
[Setting condition]
Writing 1 after reading IRQ9E2 = 0
R/W
Host IRQ6 Interrupt Enable 2
Enables or disables an HIRQ6 interrupt request
when OBF2 is set by an oDR2 write.
0: HIRQ6 interrupt request by OBF2 and IRQE6E2
is disabled
[Clearing conditions]
•
Writing 0 to IRQ6E2
•
LPC hardware reset, LPC software reset
•
Clearing OBF2 to 0 (when IEDIR2 = 0)
1: [When IEDIR2 = 0]
HIRQ6 interrupt request by setting OBF2 to 1 is
enabled
[When IEDIR2 = 1]
HIRQ6 interrupt is requested
[Setting condition]
Writing 1 after reading IRQ6E2 = 0
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