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Section 11 8-Bit Timer (TMR)
Table 11.1 (2)
Clock Input to TCNT and Count Condition (TMR_1)
TCR
CKS2
CKS1
CKS0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
1
1
1
X
Note:
* If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock
input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock
cannot be generated. Simultaneous setting of these conditions should be avoided.
[Legend]
X: Don't care
Table 11.1 (3)
Clock Input to TCNT and Count Condition (TMR_X, TMR_Y)
Channel
CKS2
TMR_Y
0
0
0
0
1
TMR_Y
0
0
0
0
1
Rev. 1.00 Mar. 12, 2008 Page 398 of 1178
REJ09B0403-0100
STCR
ICKS1
X
0
1
0
1
0
1
X
X
X
TCR
CKS1
CKS0
0
0
0
1
1
0
1
1
X
X
0
0
0
1
1
0
1
1
X
X
Description
Disables clock input
Increments at falling edge of internal clock φ/8
Increments at falling edge of internal clock φ/2
Increments at falling edge of internal clock φ/64
Increments at falling edge of internal clock φ/128
Increments at falling edge of internal clock φ/1024
Increments at falling edge of internal clock φ/2048
Increments at compare-match A from TCNT_0*
Setting prohibited
Setting prohibited
Description
Disables clock input
Increments at falling edge of internal clock φ/4
Increments at falling edge of internal clock φ/256
Increments at falling edge of internal clock φ/2048
Setting prohibited
Disables clock input
Increments at falling edge of internal clock φ
Increments at falling edge of internal clock φ/2
Increments at falling edge of internal clock φ/4
Setting prohibited
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