Advertisement
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram ................................................................................................. 3
Figure 1.2 Pin Assignments (H8S/2472 Group) ............................................................................. 4
Figure 1.3 Pin Assignments (H8S/2462 Group) ............................................................................. 5
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 27
Figure 2.2 Stack Structure in Normal Mode ................................................................................. 27
Figure 2.3 Exception Vector Table (Advanced Mode)................................................................. 28
Figure 2.4 Stack Structure in Advanced Mode ............................................................................. 29
Figure 2.5 Memory Map............................................................................................................... 30
Figure 2.6 CPU Registers ............................................................................................................. 31
Figure 2.7 Usage of General Registers ......................................................................................... 32
Figure 2.8 Stack............................................................................................................................ 33
Figure 2.9 General Register Data Formats (1).............................................................................. 36
Figure 2.9 General Register Data Formats (2).............................................................................. 37
Figure 2.10 Memory Data Formats............................................................................................... 38
Figure 2.11 Instruction Formats (Examples) ................................................................................ 50
Figure 2.12 Branch Address Specification in Memory Indirect Mode ......................................... 54
Figure 2.13 State Transitions ........................................................................................................ 58
Section 3 MCU Operating Modes
Figure 3.1 Address Map ............................................................................................................... 67
Section 4 Exception Handling
Figure 4.1 Reset Sequence............................................................................................................ 73
Figure 4.2 Stack Status after Exception Handling ........................................................................ 75
Figure 4.3 Operation When SP Value is Odd ............................................................................... 76
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller........................................................................ 78
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0 .............................................................. 87
Figure 5.3 Block Diagram of Interrupt Control Operation ........................................................... 91
Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0....... 94
Figure 5.5 State Transition in Interrupt Control Mode 1 .............................................................. 95
Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1..... 97
Figure 5.7 Interrupt Exception Handling ...................................................................................... 98
Figure 5.8 Interrupt Control for DTC ......................................................................................... 100
Figure 5.9 Conflict between Interrupt Generation and Disabling............................................... 102
Rev. 1.00 Mar. 12, 2008 Page xxix of xIviii
Advertisement
