Renesas H8S Family Hardware Manual page 75

H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Figure 2.1 Exception Vector Table (Normal Mode)
SP
PC
(16 bits)
(a) Subroutine Branch
Notes: 1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. lgnored when returning.
Figure 2.2 Stack Structure in Normal Mode
Exception vector 1
Exception vector 2
Exception vector 3
Exception vector 4
Exception vector 5
Exception vector 6
SP
2
(SP *
)
Exception
vector table
1
EXR*
, *
1 3
Reserved*
CCR
3
CCR*
PC
(16 bits)
(b) Exception Handling
Rev. 1.00 Mar. 12, 2008 Page 27 of 1178
REJ09B0403-0100
Section 2 CPU