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Section 19 LPC Interface (LPC)
19.2
Input/Output Pins
Table 19.1 lists the LPC pin configuration.
Table 19.1 Pin Configuration
Name
Abbreviation
LPC address/
LAD3 to LAD0 PE to PE0 I/O
data 3 to 0
LFRAME
LPC frame
LRESET
LPC reset
LPC clock
LCLK
Serialized
SERIRQ
interrupt request
LSCI general
LSCI
output
LSMI
LSMI general
output
PME
PME general
output
GATE A20
GA20
CLKRUN
LPC clock run
LPC power-down LPCPD
Notes: 1. Pin state monitoring input is possible in addition to the LPC interface control
input/output function.
2. Only 0 can be output. If 1 is output, the pin is in the high-impedance state, so an
external resistor is necessary to pull the signal up to VCC.
Rev. 1.00 Mar. 12, 2008 Page 668 of 1178
REJ09B0403-0100
Port
I/O
1
PE4
Input*
1
PE5
Input*
PE6
Input
1
PE7
I/O*
1,
PD0
Output*
1,
PD1
Output*
1,
PD2
Output*
1,
PD3
Output*
1,
2
PD4
I/O*
*
1
PD5
Input*
Function
Cycle type/address/data signals
serially (4-signal-line) transferred in
synchronization with LCLK
Transfer cycle start and forced
termination signal
LPC interface reset signal
33-MHz PCI clock signal
Serialized host interrupt request
signal (SMI, HIRQ1 to HIRQ15) in
synchronization with LCLK
2
*
General output
2
*
General output
2
General output
*
2
*
Gate A20 control signal output
LCLK restart request signal when
serial host interrupt is requested
LPC module shutdown signal
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