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Section 4 Exception Handling - Renesas H8S Family Hardware Manual

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4.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, interrupt, illegal instruction,
or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more
exceptions occur simultaneously, they are accepted and processed in order of priority.
Table 4.1
Exception Types and Priority
Priority
Exception Type
High
Reset
Illegal instruction
Interrupt
Trap instruction
Low

Section 4 Exception Handling

Start of Exception Handling
Starts immediately after a low-to-high transition of the RES
pin, or when the watchdog timer overflows.
Started by execution of an undefined code.
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.
Interrupt detection is not performed on completion of ANDC,
ORC, XORC, or LDC instruction execution, or on
completion of reset exception handling.
Started by execution of a trap (TRAPA) instruction. Trap
instruction exception handling requests are accepted at all
times in program execution state.
Section 4 Exception Handling
Rev. 1.00 Mar. 12, 2008 Page 69 of 1178
REJ09B0403-0100

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