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7.2.10
Event Counter Control Register (ECCR)
ECCR selects the event counter channels for use and the detection edge.
Bit
Bit Name
7
EDSB
6 to 4
—
3 to 0
ECSB3 to
ECSB0
Initial
Value
R/W
Description
0
R/W
Event Counter Edge Select
Selects the detection edge for the event counter.
0: Counts the rising edges
1: Counts the falling edges
All 0
R
Reserved
These bits are always read as 0 and cannot be modified.
All 0
R/W
Event Counter Channel Select 3 to 0
These bits select pins for event counter input. A series
of pins are selected starting from EVENT0. When
PAnDDR is set to 1, inputting events to EVENT0 to
EVENT7 is ignored.
0000: EVENT0 is used
0001: EVENT0 to EVENT1 are used
0010: EVENT0 to EVENT2 are used
0011: EVENT0 to EVENT3 are used
0100: EVENT0 to EVENT4 are used
0101: EVENT0 to EVENT5 are used
0110: EVENT0 to EVENT6 are used
0111: EVENT0 to EVENT7 are used
1000: EVENT0 to EVENT8 are used
1001: EVENT0 to EVENT9 are used
1010: EVENT0 to EVENT10 are used
1011: EVENT0 to EVENT11 are used
1100: EVENT0 to EVENT12 are used
1101: EVENT0 to EVENT13 are used
1110: EVENT0 to EVENT14 are used
1111: EVENT0 to EVENT15 are used
Section 7 Data Transfer Controller (DTC)
Rev. 1.00 Mar. 12, 2008 Page 167 of 1178
REJ09B0403-0100
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