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23.7
Usage Notes
23.7.1
Setting of Module Stop Mode
Operation of the A/D converter can be enabled or disabled by setting the module stop control
register. By default, the A/D converter is stopped. Registers of the A/D converter only become
accessible when it is released from module stop mode. See section 28, Power-Down Modes, for
details.
23.7.2
Permissible Signal Source Impedance
This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input
signal for which the signal source impedance is 5 kΩ or less. This specification is provided to
enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the
sampling time; if the sensor output impedance exceeds 5 kΩ, charging may be insufficient and it
may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is
provided externally in single mode, the input load will essentially comprise only the internal input
resistance of 10 kΩ, and the signal source impedance is ignored. However, since a low-pass filter
effect is obtained in this case, it may not be possible to follow an analog signal with a large
differential coefficient (voltage fluctuation ratio of 5 mV/µs or greater for example) (see figure
23.8). When converting a high-speed analog signal or converting in scan mode, a low-impedance
buffer should be inserted.
Sensor input
Sensor output
impedance
up to 5 kΩ
Low-pass
filter C
up to 0.1 µF
Figure 23.8 Example of Analog Input Circuit
This LSI
A/D converter equivalent circuit
10 kΩ
C
=
in
15 pF
Rev. 1.00 Mar. 12, 2008 Page 911 of 1178
Section 23 A/D Converter
20 pF
REJ09B0403-0100
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