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2.7.6
Immediate#xx:8, #xx:16, or #xx:32.................................................................... 53
2.7.7
Program-Counter Relative@(d:8, PC) or @(d:16, PC) ...................................... 53
2.7.8
Memory Indirect@@aa:8 ................................................................................... 54
2.7.9
Effective Address Calculation ................................................................................ 55
2.8
Processing States.................................................................................................................. 57
2.9
Usage Note........................................................................................................................... 59
2.9.1
Notes on Using the Bit Operation Instruction......................................................... 59
Section 3 Mcu Operating Modes ....................................................................... 61
3.1
Operating Mode Selection ................................................................................................... 61
3.2
Register Descriptions........................................................................................................... 62
3.2.1
Mode Control Register (MDCR) ............................................................................ 62
3.2.2
System Control Register (Syscr)......................................................................... 63
3.2.3
Serial Timer Control Register (Stcr) ................................................................... 64
3.3
Operating Mode Descriptions .............................................................................................. 66
3.3.1
Mode 2.................................................................................................................... 66
3.4
Address Map ........................................................................................................................ 67
Section 4 Exception Handling ............................................................................. 69
4.1
Exception Handling Types and Priority............................................................................... 69
4.2
Exception Sources And Exception Vector Table .................................................................. 70
4.3
Reset .................................................................................................................................... 72
4.3.1
Reset Exception Handling ...................................................................................... 72
4.3.2
Interrupts After Reset............................................................................................... 73
4.3.3
On-Chip Peripheral Modules after Reset is Cancelled ........................................... 73
4.4
Interrupt Exception Handling .............................................................................................. 74
4.5
Trap Instruction Exception Handling................................................................................... 74
4.6
Stack Status After Exception Handling................................................................................. 75
4.7
Usage Note........................................................................................................................... 76
Section 5 Interrupt Controller.............................................................................. 77
5.1
Features................................................................................................................................ 77
5.2
Input/Output Pins................................................................................................................. 78
5.3
Register Descriptions........................................................................................................... 79
5.3.1
Interrupt Control Registers A to D (ICRA to ICRD).............................................. 79
5.3.2
Address Break Control Register (Abrkcr) ......................................................... 80
5.3.3
Break Address Registers A To C (Bara To Barc)............................................... 81
5.3.4
Irq Sense Control Registers (Iscr16H, Iscr16L, Iscrh, Iscrl)................... 82
5.3.5
Irq Enable Registers (Ier16, Ier) ....................................................................... 84
5.3.6
Irq Status Registers (Isr16, Isr)......................................................................... 85
Rev. 1.00 Mar. 12, 2008 Page x of xIviii
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