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7.2
Register Descriptions
The DTC has the following registers.
•
DTC mode register A (MRA)
•
DTC mode register B (MRB)
•
DTC source address register (SAR)
•
DTC destination address register (DAR)
•
DTC transfer count register A (CRA)
•
DTC transfer count register B (CRB)
These six registers cannot be directly accessed from the CPU. When a DTC activation interrupt
source occurs, the DTC reads a set of register information that is stored in on-chip RAM to the
corresponding DTC registers and transfers data. After the data transfer, it writes a set of updated
register information back to on-chip RAM.
•
DTC enable registers (DTCER)
•
DTC vector register (DTVECR)
•
Keyboard comparator control register (KBCOMP)
•
Event counter control register (ECCR)
•
Event counter status register (ECS)
Section 7 Data Transfer Controller (DTC)
Rev. 1.00 Mar. 12, 2008 Page 161 of 1178
REJ09B0403-0100
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