Operation Using The Dtc - Renesas H8S Family Hardware Manual

Section 18 I

C Bus Interface (IIC)

Operation Using the DTC

This LSI provides the DTC to allow continuous data transfer. The DTC is initiated when the IRTR

flag is set to 1, which is one of the two interrupt flags (IRTR and IRIC). When the ACKE bit is 0,

the ICDRE, IRIC, and IRTR flags are set at the end of data transmission regardless of the

acknowledge bit value. When the ACKE bit is 1, the ICDRE, IRIC, and IRTR flags are set if data

transmission is completed with the acknowledge bit value of 0, and when the ACKE bit is 1, only

the IRIC flag is set if data transmission is completed with the acknowledge bit value of 1.

When initiated, DTC transfers specified number of bytes, clears the ICDRE, IRIC, and IRTR flags

to 0. Therefore, no interrupt is generated during continuous data transfer; however, if data

transmission is completed with the acknowledge bit value of 1 when the ACKE bit is 1, DTC is

not initiated, thus allowing an interrupt to be generated if enabled.

The acknowledge bit may indicate specific events such as completion of receive data processing

for some receiving devices, and for other receiving devices, the acknowledge bit may be held to 1,

indicating no specific events.

C bus format provides for selection of the slave device and transfer direction by means of

the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication

of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out

in conjunction with CPU processing by means of interrupts.

Table 18.9 shows some examples of processing using the DTC. These examples assume that the

number of transfer data bytes is known in slave mode.

Rev. 1.00 Mar. 12, 2008 Page 646 of 1178

REJ09B0403-0100