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20.3.21 Manual PAUSE Frame Set Register (MPR) ......................................................... 775
20.3.22 Automatic PAUSE Frame Retransmission Count Set Register (TPAUSER) ....... 775
20.4 Operation ........................................................................................................................... 776
20.4.1 Transmission......................................................................................................... 776
20.4.2 Reception .............................................................................................................. 779
20.4.3 RMII Frame Timing ............................................................................................. 780
20.4.4 Accessing MII Registers....................................................................................... 782
20.4.5 Magic Packet Detection ........................................................................................ 785
20.4.6 Operation by IPG Setting...................................................................................... 786
20.4.7 Flow Control......................................................................................................... 786
20.5 Usage Notes ....................................................................................................................... 788
20.5.1 Conditions for Setting LCHNG Bit ...................................................................... 788
20.5.2 Flow Control Defect 1 .......................................................................................... 788
20.5.3 Flow Control Defect 2 .......................................................................................... 788
20.5.4 Operation Seed...................................................................................................... 789
Section 21 Ethernet Controller Direct Memory Access Controller
(E-DMAC)....................................................................................... 791
21.1 Features.............................................................................................................................. 791
21.2 Register Descriptions......................................................................................................... 792
21.2.1 E-DMAC Mode Register (EDMR)....................................................................... 794
21.2.2 E-DMAC Transmit Request Register (EDTRR) .................................................. 795
21.2.3 E-DMAC Receive Request Register (EDRRR).................................................... 796
21.2.4 Transmit Descriptor List Address Register (TDLAR).......................................... 797
21.2.5 Receive Descriptor List Address Register (RDLAR) ........................................... 797
21.2.6 EtherC/E-DMAC Status Register (EESR)............................................................ 798
21.2.7 EtherC/E-DMAC Status Interrupt Permission Register (EESIPR)....................... 803
21.2.8 Transmit/Receive Status Copy Enable Register (TRSCER)................................. 806
21.2.9 Receive Missed-Frame Counter Register (RMFCR) ............................................ 808
21.2.10 Transmit FIFO Threshold Register (TFTR).......................................................... 808
21.2.11 FIFO Depth Register (FDR) ................................................................................. 810
21.2.12 Receiving method Control Register (RMCR)....................................................... 811
21.2.13 Receiving-Buffer Write Address Register (RBWAR) .......................................... 812
21.2.14 Receiving-Descriptor Fetch Address Register (RDFAR) ..................................... 812
21.2.15 Transmission-Buffer Read Address Register (TBRAR)....................................... 812
21.2.16 Transmission-Descriptor Fetch Address Register (TDFAR) ................................ 813
21.2.17 Flow Control FIFO Threshold Register (FCFTR) ................................................ 813
21.2.18 Bit Rate Setting Register (ECBRR)...................................................................... 815
21.2.19 Transmit Interrupt Register (TRIMD) .................................................................. 815
21.3 Operation ........................................................................................................................... 816
Rev. 1.00 Mar. 12, 2008 Page xxii of xIviii
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