Renesas H8S Family Hardware Manual page 793

Table 19.9 Scope of Initialization in Each LPC interface Mode

Items Initialized

LPC transfer cycle sequencer (internal state), LPCBSY and ABRT

SERIRQ transfer cycle sequencer (internal state), CLKREQ and

IRQBSY flags

LPC interface flags

(IBF1, IBF2, IBF3A, IBF3B, MWMF, C/D1, C/D2, C/D3, OBF1,

OBF2, OBF3A, OBF3B, SWMF, DBU, SMICFLG, SMICIR0, BTSR0,

BTSR1, BTIMSR, BTFVSR0, BTFVSR1), GA20 (internal state)

Host interrupt enable bits

(IRQ1E1, IRQ12E1, SMIE2, IRQ6E2, IRQ9E2 to IRQ11E2, SMIE3B,

SMIE3A, IRQ6E3, IRQ9E3 to IRQ11E3, SELREQ, IEDIR2 to

IEDIR3), Q/C flag

LPC interface operation control bits

(LPC3E to LPC1E, FGA20E, LADR1 to LADR3, IBFIE1 to IBFIE3,

PMEE, PMEB, LSMIE, LSMIB, LSCIE, LSCIB, TWRE, SELSTR3,

SELIRQ1, SELSMI, SELIRQ3 to SELIRQ15, HICR4, HICR5,

SCIFAR, HISEL, BTCSR0, BTCSR1)

LRESET signal

LPCPD signal

LAD3 to LAD0, LFRAME, LCLK, SERIRQ, CLKRUN signals

PME, LSMI, LSCI, GA20 signals (when function is selected)

PME, LSMI, LSCI, GA20 signals (when function is not selected)

Note: System reset: Reset by STBY input, RES input, or WDT overflow

LPC reset: Reset by LPC hardware reset (HR) or LPC software reset (SR)

LPC shutdown: Reset by LPC hardware shutdown (HS) or LPC software shutdown (SS)

Section 19 LPC Interface (LPC)

Initialized (0) Can be

Initialized (0) Initialized (0) Can be

Initialized (0) HR: 0

Initialized (0) Initialized (0) HS: 0

Initialized (0) Initialized (0) HS: 1

Port function Port function

Rev. 1.00 Mar. 12, 2008 Page 745 of 1178

REJ09B0403-0100