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Section 6 Bus Controller (BSC)
(2)
In Address-Data Multiplex Extended Mode
(a)
Bus Width
A bus width of 8 or 16 bits can be selected via the ABW and ABW256 bits in WSCR.
(b)
Number of Access States
Two or three states can be selected for data access via the AST and AST256 bits in WSCR. When
the 2-state access space is designated, wait-state insertion is disabled.
(c)
Wait Mode and Number of Program Wait States
• IOS Extended Area
When the IOS extended area is specified as a 3-state access space by the AST bit in WSCR,
the wait mode and the number of program wait states to be inserted automatically is selected
by the WMS1, WMS0, WC1, and WC0 bits in WSCR. Zero or one program wait state can be
inserted into address cycle. From zero to three program wait states can be selected for data
cycle.
• 256-Kbyte Extended Area
When the 256-Kbyte extended area is specified as a 3-state access space by the AST256 bit in
WSCR, the wait mode and the number of program wait states to be inserted automatically is
selected by the WMS10, WC11, and WC10 bits in WSCR2. Zero or one program wait state
can be inserted into address cycle. From zero to three program wait states can be selected for
data cycle.
The wait function for external extension is effective for connecting low-speed devices to the
external address space. However, this wait function may cause some problems when the operation
of bus masters other than the CPU, such as the DTC, are to be delayed.
Tables 6.6 to 6.11 show address-data multiplex address space and the bus specifications for the
basic bus interface of each area.
Rev. 1.00 Mar. 12, 2008 Page 120 of 1178
REJ09B0403-0100
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