Serirq Control Register 0 (Sirqcr0) - Renesas H8S Family Hardware Manual

19.3.12

SERIRQ Control Register 0 (SIRQCR0)

SIRQCR0 contains status bits that indicate the SERIRQ operating mode and bits that specify
SERIRQ interrupt sources.
Bit Bit Name Initial Value Slave Host Description
7 Q/C 0
6 SELREQ 0
5 IEDIR2 0
R/W

R Quiet/Continuous Mode Flag
Indicates the mode specified by the host at the end
of an SERIRQ transfer cycle (stop frame).
0: Continuous mode
[Clearing conditions]
•
LPC hardware reset, LPC software reset
•
Specification by SERIRQ transfer cycle stop
frame
1: Quiet mode
[Setting condition]
Specification by SERIRQ transfer cycle stop frame.

R/W Start Frame Initiation Request Select
Selects the condition of a start frame initiation
request when a host interrupt request is cleared in
quiet mode.
0: Start frame initiation is requested when all
interrupt requests are cleared
1: Start frame initiation is requested when one or
more interrupt requests are cleared

R/W Interrupt Enable Direct Mode
Specifies whether LPC channel 2 and channel 3
SERIRQ interrupt source (SMI, IRQ6, IRQ9 to
IRQ11) generation is conditional upon OBF, or is
controlled only by the host interrupt enable bit.
0: Host interrupt is requested when host interrupt
enable and corresponding OBF bits are both set to
1
1: Host interrupt is requested when host interrupt
enable bit is set to 1
Section 19 LPC Interface (LPC)
Rev. 1.00 Mar. 12, 2008 Page 699 of 1178
REJ09B0403-0100