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Bit
Bit Name
0
SWR
21.2.2
E-DMAC Transmit Request Register (EDTRR)
The EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC.
When transmission of one frame is completed, the next descriptor is read. If the transmit
descriptor active bit in this descriptor has the "active" setting, transmission is continued. If the
transmit descriptor active bit has the "inactive" setting, the TR bit is cleared and operation of the
transmit DMAC is halted.
Bit
Bit Name
31 to 1
0
TR
Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
value
R/W
Description
0
R/W
Software Reset
Writing 1 in this bit initializes registers of the E-DMAC
other than TDLAR, RDLAR, RMFCR, and ECBRR, and
registers of the EtherC. While a software reset is issued
(for 64 states), accesses to the all Ethernet-related
registers are prohibited.
Software reset period (example):
When φ = 34 MHz: 1.88 µs
This bit is always read as 0.
0: Writing 0 is ignored (E-DMAC operation is not
affected)
1: Writing 1 resets the EtherC and E-DMAC and then
automatically cleared
Initial
value
R/W
Description
All 0
R
Reserved
These bits are always read as 0. The initial value
should not be changed.
0
R/W
Transmit Request
Check TR = 0 before transmission is started.
0: Transmission-halted state. Writing 0 does not stop
transmission. Termination of transmission is
controlled by the active bit in the transmit descriptor
1: Start of transmission. The relevant descriptor is read
and a frame is sent with the transmit active bit set to
1
Rev. 1.00 Mar. 12, 2008 Page 795 of 1178
REJ09B0403-0100
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