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Section 8 I/O Ports
8.2.10
Port A
Port A is an 8-bit I/O port. Port A pins can also function as the address output, event counter input,
interrupt input, and EtherC control input/output pins. Port A has the following registers. PADDR
and PAPIN are allocated to the same address.
• Port A data direction register (PADDR)
• Port A output data register (PAODR)
• Port A input data register (PAPIN)
(1)
Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the port A pins.
Bit
Bit Name
7
PA7DDR
6
PA6DDR
5
PA5DDR
4
PA4DDR
3
PA3DDR
2
PA2DDR
1
PA1DDR
0
PA0DDR
Rev. 1.00 Mar. 12, 2008 Page 322 of 1178
REJ09B0403-0100
Initial Value
R/W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
0
W
Description
When set to 1, the corresponding pins function as
output port pins; when cleared to 0, function as input
port pins.
As the address of this register is the same as that of
PAPIN, reading from this register indicates the state
of port A.
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