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Section 8 I/O Ports
• PA4/ExIRQ4/EVENT4/A20, PA3/ExIRQ3/EVENT3/A19, PA2/ExIRQ2/EVENT2/A18
The pin function is switched as shown below according to the setting of address 18 and the
PAnDDR bit.
Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin.
When using the pin as the ExIRQn input or an EVENT input pin, clear the PAnDDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 when
using the pin as the PAn or Am output pin.
PAnDDR
Address 18
Pin function
ExIRQn input pin/EVENTn input pin
[Legend] n = 4 to 2, m = 20 to 18, X: Don't care.
• PA1/ExIRQ1/EVENT1/A17, PA0/ExIRQ0/EVENT0/A16
The pin function is switched as shown below according to the setting of address 13 and the
PAnDDR bit.
Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin.
When using the pin as the ExIRQn input, clear the PAnDDR bit to 0. When using the pin as an
EVENT input pin, clear the PAnDDR bit to 0. Though the settings for the EVENT input pin
have been made, set the PAnDDR bit to 1 when using the pin as the PAn or Am output pin.
PAnDDR
Address 13
Pin function
ExIRQn input pin/EVENTn input pin
[Legend]
n = 1, 0; m = 17, 16, X: Don't care.
Rev. 1.00 Mar. 12, 2008 Page 326 of 1178
REJ09B0403-0100
0
X
PAn input pin
0
X
PAn input pin
1
1
PAn output pin
1
1
PAn output pin
1
0
Am output pin
0
Am output pin
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