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Section 22 USB Function Module (USB)
22.3.1
Interrupt Flag Register 0 (IFR0)
IFR0, together with interrupt flag registers 1and 2 (IFR1and IFR2), indicates interrupt status
information required by the application. When an interrupt source is generated, the corresponding
bit is set to 1. And then this bit, in combination with interrupt enable register 0 (IER0), generates
an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
However, since EP1FULL and EP2EMPTY are status bits, these bits cannot be cleared.
Bit
Bit Name
7
BRST
6
EP1FULL
5
EP2TR
Rev. 1.00 Mar. 12, 2008 Page 836 of 1178
REJ09B0403-0100
Initial
Value
R/W
Description
0
R/W
Bus Reset
This bit is set to 1 when a bus reset signal is detected on
the USB bus.
0
R/W
EP1 FIFO Full
[Reading]
This bit is set when endpoint 1 receives one packet of
data successfully from the host, and holds a value of 1
as long as there is valid data in the FIFO buffer. This bit
cannot be cleared.
[Writing]
When the data in endpoint 1 is transferred by the DTC,
writing 0 to this bit clears the request for a DTC transfer
end interrupt. If the DTC transfer is not used, always
write 1 to this bit.
0
R/W
EP2 Transfer Request
This bit is set if there is no valid transmit data in the FIFO
buffer when an IN token for endpoint 2 is received from
the host. A NAK handshake is returned to the host until
data is written to the FIFO buffer and packet
transmission is enabled.
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