Interrupt Enable Register 2 (Ier2) - Renesas H8S Family Hardware Manual

22.3.9

Interrupt Enable Register 2 (IER2)

IER2 enables the interrupt requests of interrupt flag register 2 (IFR2). When an interrupt flag is set
to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the
CPU. The interrupt vector number is determined by the contents of interrupt select register 2
(ISR2).
Bit Bit Name
7 SSRSME

6, 5
4 SURSE
3 CFDN
2 SOF
1 SETCE
0 SETIE
22.3.10 EP0i Data Register (EPDR0i)
EPDR0i is an 8-byte transmit FIFO buffer for endpoint 0. EPDR0i holds one packet of transmit
data for control-in. Transmit data is fixed by writing one packet of data and setting EP0iPKTE in
the trigger register. When an ACK handshake is returned from the host after the data has been
transmitted, EP0iTS in interrupt flag register 0 is set. This FIFO buffer can be initialized by means
of EP0iCLR in the FCLR register.
Bit Bit Name
7 to 0 D7 to D0
Initial
Value R/W Description
0 R/W Resume Detection for Software Standby Cancel
For the details of the operation, see section 22.5.3,
Suspend and Resume Operations.
All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
0 R/W Suspend/Resume Detection
For the details of the operation, see section 22.5.3,
Suspend and Resume Operations.
0 R/W End Point Information Load End
0 R/W SOF Interrupt Detection
0 R/W Set_Configuration Command Detection
0 R/W Set_Interface Command Detection
Initial
Value
R/W Description
Undefined W Data register for control-in transfer
Section 22 USB Function Module (USB)
Rev. 1.00 Mar. 12, 2008 Page 843 of 1178
REJ09B0403-0100