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Section 11 8-Bit Timer (TMR)
11.2
Register Descriptions
The TMR has the following registers for each channel. For details on the serial timer control
register, see section 3.2.3, Serial Timer Control Register (STCR).
• Timer counter (TCNT)
• Time constant register A (TCORA)
• Time constant register B (TCORB)
• Timer control register (TCR)
• Timer control/status register (TCSR)
• Timer connection register S (TCONRS)*
Notes:
Some of the registers of TMR_X and TMR_Y use the same address. The registers can
be switched by the TMRX/Y bit in TCONRS.
* TCONRS is only provided for TMR_X
11.2.1
Timer Counter (TCNT)
Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16-
bit register, so they can be accessed together by word access. The clock source is selected by the
CKS2 to CKS0 bits in TCR. TCNT can be cleared by a compare-match A signal or compare-
match B signal. The method of clearing can be selected by the CCLR1 and CCLR0 bits in TCR.
When TCNT overflows (changes from H'FF to H'00), the OVF bit in TCSR is set to 1. TCNT is
initialized to H'00.
TCNT_Y can be accessed when the TMRX/Y bit in TCONRS is 1. TCNT_X can be accessed
when the TMRX/Y bit in TCONRS is 0. See section 11.2.6, Timer Connection Register S
(TCONRS).
Rev. 1.00 Mar. 12, 2008 Page 394 of 1178
REJ09B0403-0100
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