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Section 19 LPC Interface (LPC)
19.3.5
Pin Function Control Register (PINFNCR)
PINFNCR selects whether the pins of the associated port are used for the LPC function or general
I/O.
Bit
Bit Name
7 to 3
2
SERIRQOFF
1
LPCPDOFF
0
CLKRUNOFF
19.3.6
LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L)
LADR12H and LADR12L are temporary registers for accessing internal registers LADR1H,
LADR1L, LADR2H, and LADR2L.
When the LADR12SEL bit in HICR4 is 0, LPC channel 1 host addresses (LADR1H, LADR1L)
are set through LADR12. The contents of the address field in LADR1 must not be changed while
channel 1 is operating (while LPC1E is set to 1).
When the LADR12SEL bit is 1, LPC channel 2 host addresses (LADR2H, LADR2L) are set
through LADR12. The contents of the address field in LADR2 must not be changed while channel
2 is operating (while LPC2E is set to 1).
Table 19.2 shows the initial value of each register. Table 19.3 shows the host register selection in
address match determination. Table 19.4 shows the slave selection internal registers in slave (this
LSI) access.
Table 19.2 LADR1, LADR2 Initial Values
Register Name
LADR1
LADR2
Rev. 1.00 Mar. 12, 2008 Page 684 of 1178
REJ09B0403-0100
R/W
Initial
Value
Slave Host Description
All 0
R/W
0
R/W
0
R/W
0
R/W
Initial Value
H'0060
H'0062
Reserved
The initial value bit should not be changed.
0: SERIRQ pin
1: General I/O port
0: LPCPD pin
1: General I/O port
0: CLKRUN pin
1: General I/O port
Description
I/O address of channel 1
I/O address of channel 2
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