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Figure 18.29 Notes on Reading Master Receive Data ................................................................ 656
Figure 18.30 Flowchart for Start Condition Issuance Instruction
for Retransmission and Timing ............................................................................. 657
Figure 18.31 Stop Condition Issuance Timing ........................................................................... 658
Figure 18.32 IRIC Flag Clearing Timing When WAIT = 1 ....................................................... 659
Figure 18.33 ICDR Register Read and ICCR Register Access Timing in
Slave Transmit Mode ............................................................................................ 660
Figure 18.34 TRS Bit Set Timing in Slave Mode....................................................................... 661
Figure 18.35 Diagram of Erroneous Operation when Arbitration Lost ...................................... 663
Section 19 LPC Interface (LPC)
Figure 19.1 Block Diagram of LPC............................................................................................ 667
Figure 19.2 Typical LFRAME Timing....................................................................................... 735
Figure 19.3 Abort Mechanism.................................................................................................... 735
Figure 19.4 SMIC Write Transfer Flow ..................................................................................... 736
Figure 19.5 SMIC Read Transfer Flow ...................................................................................... 737
Figure 19.6 BT Write Transfer Flow .......................................................................................... 738
Figure 19.7 BT Read Transfer Flow........................................................................................... 739
Figure 19.8 GA20 Output........................................................................................................... 741
Figure 19.9 Power-Down State Termination Timing ................................................................. 746
Figure 19.10 SERIRQ Timing.................................................................................................... 747
Figure 19.11 Clock Start Request Timing .................................................................................. 749
Figure 19.12 HIRQ Flowchart (Example of Channel 1)............................................................. 753
Section 20 Ethernet Controller (EtherC)
Figure 20.1 Configuration of EtherC.......................................................................................... 758
Figure 20.2 EtherC Transmitter State Transitions ...................................................................... 777
Figure 20.3 EtherC Receiver State Transmissions ..................................................................... 779
Figure 20.4 RMII Frame Transmit Timing (Normal Transmission)........................................... 780
Figure 20.5 RMII Frame Receive Timing (Normal Reception) ................................................. 780
Figure 20.6 RMII Frame Receive Timing (Reception with False Carrier)................................. 781
Figure 20.7 MII Management Frame Format ............................................................................. 782
Figure 20.8 1-Bit Data Write Flowchart..................................................................................... 783
Figure 20.9 Bus Release Flowchart (TA in Read in Figure 20.7)............................................... 783
Figure 20.10 1-Bit Data Read Flowchart.................................................................................... 784
Figure 20.11 Independent Bus Release Flowchart (IDLE in Write in Figure 20.7) ................... 784
Figure 20.12 Changing IPG and Transmission Efficiency ......................................................... 786
Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Figure 21.1 Configuration of E-DMAC, and Descriptors and Buffers....................................... 792
Figure 21.2 Relationship between Transmit Descriptor and Transmit Buffer............................ 817
Figure 21.3 Relationship between Receive Descriptor and Receive Buffer ............................... 821
Rev. 1.00 Mar. 12, 2008 Page xxxvi of xIviii
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