Advertisement
Bit
Bit Name
2 to 0
CKS2 to
CKS0
Notes: 1. Only 0 can be written to clear the flag.
2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at
least twice.
Initial
Value
R/W
Description
All 0
R/W
Clock Select 2 to 0
Select the clock source to be input to TCNT. The overflow
cycle for φ = 34 MHz and φSUB = 32.768 kHz is enclosed
in parentheses.
When PSS = 0:
000: φ/2 (cycle: 15.1 µs)
001: φ/64 (cycle: 481.9 µs)
010: φ/128 (cycle: 963.8 µs)
011: φ/512 (cycle: 3.856 ms)
100: φ/2048 (cycle: 15.42 ms)
101: φ/8192 (cycle: 61.68 ms)
110: φ/32768 (cycle: 246.7 ms)
111: φ/131072 (cycle: 986.9 ms)
When PSS = 1:
000: φSUB/2 (cycle: 15.6 ms)
001: φSUB/4 (cycle: 31.3 ms)
010: φSUB/8 (cycle: 62.5 ms)
011: φSUB/16 (cycle: 125 ms)
100: φSUB/32 (cycle: 250 ms)
101: φSUB/64 (cycle: 500 ms)
110: φSUB/128 (cycle: 1 s)
111: φSUB/256 (cycle: 2 s)
Section 12 Watchdog Timer (WDT)
Rev. 1.00 Mar. 12, 2008 Page 419 of 1178
REJ09B0403-0100
Advertisement
