Smic Control Status Register (Smiccsr) - Renesas H8S Family Hardware Manual

Section 19 LPC Interface (LPC)

Bit Name Initial Value Slave Host Description

Note: Only 0 can be written to clear the flag.

19.3.21 SMIC Control Status Register (SMICCSR)

SMICCSR is one of the registers used to implement SMIC mode. This is an 8-bit

readable/writable register that stores a control code issued from the host and a status code that is

returned from the slave.

The control code is written to this register accompanied by the transfer between the host and slave.

The status code is returned to this register to indicate that the slave has recognized the control

code, and a specified transfer cycle has been completed.

19.3.22 SMIC Data Register (SMICDTR)

SMICDTR is one of the registers used to implement SMIC mode. This is an 8-bit register that is

accessible (readable/writable) from both the slave processor (this LSI) and host processor. This is

used for data transfer between the host and slave.

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The initial value should not be changed.

This bit indicates that the slave is now transferring

data. This bit can be cleared only by the slave and

set only by the host.

The rising edge of this bit is a source of internal

interrupt to the slave.

0: Transfer cycle wait state

[Clearing conditions]

After the slave reads BUSY = 1, writes 0 to this bit.

1: Transfer cycle in progress

[Setting condition]

When the host writes 1 to this bit.