Usage Notes - Renesas H8S Family Hardware Manual

18.6

1. In master mode, if an instruction to generate a start condition is immediately followed by an

instruction to generate a stop condition, neither condition will be output correctly. To output

consecutive start and stop conditions*, after issuing the instruction that generates the start

condition, read the relevant DR registers of I

both low. If the ICE bit is set to 1, pin state can be monitored by reading DR register. Then

issue the instruction that generates the stop condition. Note that SCL may not yet have gone

low when BBSY is cleared to 0.

Note: * An illegal procedure in the I

2. Either of the following two conditions will start the next transfer. Pay attention to these

conditions when accessing to ICDR.

 Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to

 Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to

3. Table 18.11 shows the timing of SCL and SDA outputs in synchronization with the internal

clock. Timings on the bus are determined by the rise and fall times of signals affected by the

bus load capacitance, series resistance, and parallel resistance.

Table 18.11 I

C Bus Timing (SCL and SDA Outputs)

SCL output cycle time

SCL output high pulse width

SCL output low pulse width

SDA output bus free time

Start condition output hold time

Retransmission start condition output

Stop condition output setup time

Data output setup time (master)

Data output setup time (slave)

Data output hold time

when IICXn is 0, 12 t

C bus output pins, check that SCL and SDA are

C bus specification.

Symbol Output Timing

when IICXn is 1 (n = 0 to 5).

Section 18 I

Rev. 1.00 Mar. 12, 2008 Page 651 of 1178

C Bus Interface (IIC)

REJ09B0403-0100