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Section 20 Ethernet Controller (EtherC)
20.3.3
EtherC Interrupt Permission Register (ECSIPR)
ECSIPR is a 32-bit readable/writable register that enables or disables the interrupt sources
indicated by ECSR. Each bit can disable or enable interrupts corresponding to the bits in ECSR.
Bit
Bit Name
31 to 5
4
PSRTOIP
3
—
2
LCHNGIP
1
MPDIP
0
ICDIP
Rev. 1.00 Mar. 12, 2008 Page 766 of 1178
REJ09B0403-0100
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0. The initial value
should not be changed.
0
R/W
PAUSE Frame Retransmission Retry Over Interrupt
Enable
0: Interrupt notification by the PSRTO bit is disabled
1: Interrupt notification by the PSRTO bit is enabled
0
R
Reserved
This bit is always read as 0. The initial value should
not be changed.
0
R/W
LINK Signal Changed Interrupt Enable
0: Interrupt notification by the LCHNG bit is disabled
1: Interrupt notification by the LCHNG bit is enabled
0
R/W
Magic Packet Detection Interrupt Enable
0: Interrupt notification by the MPD bit is disabled
1: Interrupt notification by the MPD bit is enabled
0
R/W
Illegal Carrier Detection Interrupt Enable
0: Interrupt notification by the ICD bit is disabled
1: Interrupt notification by the ICD bit is enabled
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