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SCL
8
9
(master output)
SDA
Bit 0
(master output)
Data 1
[7]
SDA
A
(slave output)
ICDRE
IRIC
IRTR
ICDR
Data 1
User processing
[9] ICDR write
Figure 18.9 Stop Condition Issuance Operation Timing Example in Master Transmit Mode
18.4.4
Master Receive Operation
2
In I
C bus format master receive mode, the master device outputs the receive clock, receives data,
and returns an acknowledge signal. The slave device transmits data.
The master device transmits data containing the slave address and R/W (1: read) in the first frame
following the start condition issuance in master transmit mode, selects the slave device, and then
switches the mode for receive operation.
1
2
3
4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Data 2
[9] IRIC clear
(MLS = WAIT = 0)
Section 18 I
5
6
7
8
9
Bit 2
Bit 1
Bit 0
[10]
A
Data 2
[11] ACKB read
[12] IRIC clear
Rev. 1.00 Mar. 12, 2008 Page 623 of 1178
2
C Bus Interface (IIC)
Stop condition issuance
[12] BBSY set to 1 and
SCP cleared to 0
(Stop condition issuance)
REJ09B0403-0100
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