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Address bus
Figure 6.31 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0)
6.6.2
Wait Control
As with the basic bus interface, program wait insertion or pin wait insertion using the WAIT pin is
possible in the initial cycle (full access) of the burst ROM interface. For details, see section 6.5.6,
Wait Control. Wait states cannot be inserted in a burst cycle.
Full access
T
1
φ
AS/IOS
(IOSE = 0)
RD
Data bus
Read data
Burst access
T
T
T
2
1
1
Only lower
address changes
Read data Read data
Rev. 1.00 Mar. 12, 2008 Page 153 of 1178
Section 6 Bus Controller (BSC)
REJ09B0403-0100
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