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Section 23 A/D Converter
AVCC
AVref
10-bit D/A
AVSS
AN0
AN1
AN2
AN3
AN4
Sample-and-hold
AN5
circuit
AN6
AN7
ADTRG
[Legend]
ADCR: A/D control register
ADCSR: A/D control/status register
ADDRA: A/D data register A
ADDRB: A/D data register B
ADDRC: A/D data register C
Rev. 1.00 Mar. 12, 2008 Page 896 of 1178
REJ09B0403-0100
A
A
D
D
D
D
R
R
A
B
+
Comparator
ADDRD: A/D data register D
ADDRE: A/D data register E
ADDRF: A/D data register F
ADDRG: A/D data register G
ADDRH: A/D data register H
Figure 23.1 Block Diagram of the A/D Converter
Module data bus
A
A
A
A
A
A
D
D
D
D
D
D
D
D
D
D
D
D
R
R
R
R
R
R
C
D
E
F
G
H
Control circuit
Internal data
bus
A
A
D
D
C
C
S
R
R
ADI interrupt
signal
Conversion start trigger
from TMR_0
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