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Section 15 Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
3
FE
2
PE
Rev. 1.00 Mar. 12, 2008 Page 520 of 1178
REJ09B0403-0100
Initial Value R/W
0
R
0
R
Description
Framing Error
Indicates that the stop bit of the receive data is
invalid. When the FIFO is enabled, this error occurs
in any receive data in the FIFO, and this bit is set
when the receive data is in the first FIFO buffer. The
UART attempts resynchronization after a framing
error occurs. The UART, which assumes that the
framing error is due to the next start bit, samples the
start bit and treats it as a start bit.
0: No framing error
[Clearing condition]
FLSR read
1: A framing error
[Setting condition]
Invalid stop bit in the receive data
Parity Error
This bit indicates a parity error in the receive data
when the PEN bit in FLCR is 1. When the FIFO is
enabled, this error occurs in any receive data in the
FIFO, and this bit is set when the receive data is in
the first FIFO buffer.
0: No parity error
[Clearing condition]
FLSR read
If this bit is set during an overrun error, read FLSR
twice.
1: A parity error
[Setting condition]
Detection of parity error in receive data
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