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Figure 17.17 Flowchart Example of Simultaneous Transmission/Reception
(Clock Synchronous Communication Mode) ........................................................ 582
2
Section 18 I
C Bus Interface (IIC)
Figure 18.1 Block Diagram of I
2
Figure 18.2 I
C Bus Interface Connections (Example: This LSI as Master) .............................. 587
2
Figure 18.3 I
C Bus Data Formats (I
2
Figure 18.4 I
C Bus Data Formats (Serial Formats) ................................................................... 617
2
Figure 18.5 I
C Bus Timing........................................................................................................ 618
Figure 18.6 Sample Flowchart for IIC Initialization................................................................... 619
Figure 18.7 Sample Flowchart for Operations in Master Transmit Mode .................................. 620
Figure 18.8 Operation Timing Example in Master Transmit Mode (MLS = WAIT = 0)........... 622
Figure 18.9 Stop Condition Issuance Operation Timing Example in Master Transmit Mode
(MLS = WAIT = 0)................................................................................................. 623
Figure 18.10 Sample Flowchart for Operations in Master Receive Mode (HNDS = 1) ............. 624
Figure 18.11 Master Receive Mode Operation Timing Example
(MLS = WAIT = 0, HNDS = 1)............................................................................ 626
Figure 18.12 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1)............................................................................ 626
Figure 18.13 Sample Flowchart for Operations in Master Receive Mode
(receiving multiple bytes) (WAIT = 1) ................................................................. 627
Figure 18.14 Sample Flowchart for Operations in Master Receive Mode
(receiving a single byte) (WAIT = 1).................................................................... 628
Figure 18.15 Master Receive Mode Operation Timing Example
(MLS = ACKB = 0, WAIT = 1)............................................................................ 631
Figure 18.16 Stop Condition Issuance Timing Example in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1)............................................................................ 631
Figure 18.17 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 1) ............... 633
Figure 18.18 Slave Receive Mode Operation Timing Example (1) (MLS = 0, HNDS= 1)........ 635
Figure 18.19 Slave Receive Mode Operation Timing Example (2) (MLS = 0, HNDS= 1)........ 635
Figure 18.20 Sample Flowchart for Operations in Slave Receive Mode (HNDS = 0) ............... 636
Figure 18.21 Slave Receive Mode Operation Timing Example (1)
(MLS = ACKB = 0, HNDS = 0) ........................................................................... 638
Figure 18.22 Slave Receive Mode Operation Timing Example (2)
(MLS = ACKB = 0, HNDS = 0) ........................................................................... 639
Figure 18.23 Sample Flowchart for Slave Transmit Mode......................................................... 640
Figure 18.24 Slave Transmit Mode Operation Timing Example (MLS = 0).............................. 642
Figure 18.25 IRIC Setting Timing and SCL Control (1) ............................................................ 643
Figure 18.26 IRIC Setting Timing and SCL Control (2) ............................................................ 644
Figure 18.27 IRIC Setting Timing and SCL Control (3) ............................................................ 645
Figure 18.28 Block Diagram of Noise Canceler......................................................................... 648
2
C Bus Interface........................................................................ 586
2
C Bus Formats)................................................................ 617
Rev. 1.00 Mar. 12, 2008 Page xxxv of xIviii
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