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Section 7 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software, to transfer data.
Figure 7.1 shows a block diagram of the DTC. The DTC's register information is stored in the on-
chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus
connects the DTC to addresses H'FFEC00 to H'FFEFFF in on-chip RAM (1 kbyte), enabling 32-
bit/1-state reading and writing of the DTC register information.
7.1
Features
•
Transfer is possible over any number of channels
•
Three transfer modes
Normal, repeat, and block transfer modes are available
•
One activation source can trigger a number of data transfers (chain transfer)
•
Direct specification of 16 Mbytes address space is possible
•
Activation by software is possible
•
Transfer can be set in byte or word units
•
A CPU interrupt can be requested for the interrupt that activated the DTC
•
Module stop mode can be set
•
DTC operates in high-speed mode even when the LSI is in medium-speed mode
Section 7 Data Transfer Controller (DTC)
Rev. 1.00 Mar. 12, 2008 Page 159 of 1178
REJ09B0403-0100
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