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Section 10 16-Bit Free-Running Timer (FRT)
10.5.2
Conflict between FRC Write and Increment
If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes
priority and FRC is not incremented. Figure 10.9 shows the timing for this type of conflict.
Figure 10.9 Conflict between FRC Write and Increment
Rev. 1.00 Mar. 12, 2008 Page 386 of 1178
REJ09B0403-0100
Write cycle of FRC
T 1
φ
Address
Internal write
signal
FRC input
clock
FRC
T 2
FRC address
N
Write data
M
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