Bus Mastership Transfer Timing - Renesas H8S Family Hardware Manual

Section 6 Bus Controller (BSC)

Bus Mastership Transfer Timing

When a bus request is received from a bus master with a higher priority than that of the bus master

that has acquired the bus mastership and is currently operating, the bus mastership is not

necessarily transferred immediately. Each bus master can relinquish the bus mastership at the

timings given below.

The CPU is the lowest-priority bus master, and if a bus mastership request is received from the

DTC or E-DMAC, the bus arbiter transfers the bus mastership to the DTC or E-DMAC. The

timing for transferring the bus mastership is as follows:

• Timing for transferring the bus mastership to the DTC

1. Bus mastership is transferred at a break between bus cycles. However, if bus cycle is executed

in discrete operations, as in the case of a longword size access, the bus is not transferred at a

break between the operations. For details, see section 2.7, Bus States During Instruction

Execution in the H8S/2600 Series, H8S/2000 Series Software Manual.

2. If the CPU is in sleep mode, it transfers the bus mastership immediately.

• Timing for transferring the bus mastership to the E-DMAC

1. Bus mastership is transferred at a break between bus cycles. Even if bus cycle is executed in

discrete operations, as in the case of a longword size access, the bus can be transferred at a

break between bus cycles. For details, see section 21, Ethernet Controller Direct Memory

Access Controller (E-DMAC).

2. If the CPU is in sleep mode, it transfers the bus mastership immediately.

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