Advertisement
Bit
Bit Name
4
EP2EMPTY
3
SETUPTS
2
EP0oTS
1
EP0iTR
0
EP0iTS
Initial
Value
R/W
Description
1
R/(W)
EP2 FIFO Empty
[Reading]
This bit is set when at least one of the dual endpoint 2
transmit FIFO buffers is ready for transmit data to be
written. This bit cannot be cleared.
[Writing]
When the data in endpoint 2 is transferred by the DTC,
writing 0 to this bit clears the request for a DTC transfer
end interrupt. If the DTC transfer is not used, always
write 1 to this bit.
0
R/W
Setup Command Receive Complete
This bit is set to 1 when endpoint 0 receives successfully
a setup command requiring decoding on the application
side, and returns an ACK handshake to the host.
0
R/W
EP0o Receive Complete
This bit is set to 1 when endpoint 0 receives data from
the host successfully, stores the data in the FIFO buffer,
and returns an ACK handshake to the host.
0
R/W
EP0i Transfer Request
This bit is set if there is no valid transmit data in the FIFO
buffer when an IN token for endpoint 0 is received from
the host. A NAK handshake is returned to the host until
data is written to the FIFO buffer and packet
transmission is enabled.
0
R/W
EP0i Transmit Complete
This bit is set when data is transmitted to the host from
endpoint 0 and an ACK handshake is returned.
Section 22 USB Function Module (USB)
Rev. 1.00 Mar. 12, 2008 Page 837 of 1178
REJ09B0403-0100
Advertisement
