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Bit
Bit Name
29
TFP1
28
TFP0
27
TFE
26 to 0
TFS26 to
TFS0
Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Initial
value
R/W
Description
0
R/W
Transmit Frame Position 1, 0
0
R/W
These two bits specify the relationship between the
transmit buffer and transmit frame. In the preceding
and following descriptors, a logically positive
relationship must be maintained between the settings
of this bit and the TDLE bit.
00: Frame transmission for transmit buffer indicated
01: Transmit buffer indicated by this descriptor
10: Transmit buffer indicated by this descriptor is start
11: Contents of transmit buffer indicated by this
0
R/W
Transmit Frame Error
Indicates that one or other bit of the transmit frame
status indicated by bits 26 to 0 is set. Whether or not
the transmit frame status information is copied into
this bit is specified by the transmit/receive status copy
enable register.
0: No error during transmission
1: An error occurred during transmission
All 0
R/W
Transmit Frame Status
TFS26 to TFS4: Reserved (The initial value should
TFS3: Carrier Not Detect (corresponds to CND bit in
TFS2: Detect Loss of Carrier (corresponds to DLC bit
TFS1: Delayed collision Detect (corresponds to CD
TFS0: Transmit Retry Over (corresponds to TRO bit
by this descriptor continues (frame is not
concluded)
contains end of frame (frame is concluded)
of frame (frame is not concluded)
descriptor are equivalent to one frame (one
frame/one buffer)
not be changed.)
EESR)
in EESR)
bit in EESR)
in EESR)
Rev. 1.00 Mar. 12, 2008 Page 819 of 1178
REJ09B0403-0100
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