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11.6.2
Conflict between TCNT Write and Increment
If a TCNT input clock is generated during the T
11.8, the write takes priority and the counter is not incremented.
φ
Address
Internal write signal
TCNT input clock
TCNT
Figure 11.8 Conflict between TCNT Write and Increment
state of a TCNT write cycle as shown in figure
2
TCNT write cycle by CPU
T 1
T 2
TCNT address
N
Section 11 8-Bit Timer (TMR)
M
Counter write data
Rev. 1.00 Mar. 12, 2008 Page 409 of 1178
REJ09B0403-0100
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