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19.4.1 LPC interface Activation ...................................................................................... 733
19.4.2 LPC I/O Cycles..................................................................................................... 733
19.4.3 SMIC Mode Transfer Flow................................................................................... 735
19.4.4 BT Mode Transfer Flow ....................................................................................... 738
19.4.5 Gate A20............................................................................................................... 740
19.4.6 LPC Interface Shutdown Function (LPCPD)........................................................ 743
19.4.7 LPC Interface Serialized Interrupt Operation (SERIRQ) ..................................... 747
19.4.8 LPC Interface Clock Start Request ....................................................................... 749
19.4.9 SCIF Control from LPC Interface......................................................................... 749
19.5 Interrupt Sources................................................................................................................ 750
19.5.1 IBFI1, IBFI2, IBFI3, and ERRI ............................................................................ 750
19.5.2 SMI, HIRQ1, HIRQ3, HIRQ4, HIRQ5, HIRQ6, HIRQ7, HIRQ8, HIRQ9,
HIRQ10, HIRQ11, HIRQ12, HIRQ13, HIRQ14, and HIRQ15............................ 751
19.6 Usage Note......................................................................................................................... 754
19.6.1 Data Conflict......................................................................................................... 754
Section 20 Ethernet Controller (Etherc)............................................................757
20.1 Features.............................................................................................................................. 757
20.2 Input/Output Pins ............................................................................................................... 759
20.3 Register Description........................................................................................................... 760
20.3.1 EtherC Mode Register (ECMR)............................................................................ 761
20.3.2 EtherC Status Register (ECSR) ............................................................................ 764
20.3.3 EtherC Interrupt Permission Register (ECSIPR) .................................................. 766
20.3.4 PHY Interface Register (PIR) ............................................................................... 767
20.3.5 MAC Address High Register (MAHR) ................................................................ 768
20.3.6 MAC Address Low Register (MALR).................................................................. 768
20.3.7 Receive Frame Length Register (RFLR) .............................................................. 769
20.3.8 PHY Status Register (PSR)................................................................................... 770
20.3.9 Transmit Retry Over Counter Register (TROCR) ................................................ 770
20.3.10 Delayed Collision Detect Counter Register (CDCR)............................................ 771
20.3.11 Lost Carrier Counter Register (LCCR)................................................................. 771
20.3.12 Carrier Not Detect Counter Register (CNDCR) ................................................... 771
20.3.13 CRC Error Frame Counter Register (CEFCR)...................................................... 772
20.3.14 Frame Receive Error Counter Register (FRECR)................................................. 772
20.3.15 Too-Short Frame Receive Counter Register (TSFRCR)....................................... 772
20.3.16 Too-Long Frame Receive Counter Register (TLFRCR)....................................... 773
20.3.17 Residual-Bit Frame Counter Register (RFCR) ..................................................... 773
20.3.18 Multicast Address Frame Counter Register (MAFCR)......................................... 773
20.3.19 IPG Register (IPGR)............................................................................................. 774
20.3.20 Automatic PAUSE Frame Set Register (APR) ..................................................... 774
Rev. 1.00 Mar. 12, 2008 Page xxi of xIviii
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