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19.3.8
Input Data Registers 1 to 3 (IDR1 to IDR3)
The IDR registers are 8-bit read-only registers to the slave processor (this LSI), and 8-bit write-
only registers to the host processor. The registers selected from the host according to the I/O
address are described in the following sections: for information on IDR1 and IDR2 selection, see
section 19.3.6, LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L), and for
information on IDR3 selection, see section 19.3.7, LPC Channel 3 Address Register H, L
(LADR3H, LADR3L). Data transferred in an LPC I/O write cycle is written to the selected
register. The state of bit 2 of the I/O address is latched into the C/D bit in STR, to indicate whether
the written information is a command or data.
The initial values of the IDR registers are undefined.
19.3.9
Output Data Registers 0 to 3 (ODR1 to ODR3)
The ODR registers are 8-bit readable/writable registers to the slave processor (this LSI), and 8-bit
read-only registers to the host processor. The registers selected from the host according to the I/O
address are described in the following sections: for information on ODR1 and ODR2 selection, see
section 19.3.6, LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L), and for
information on ODR3 selection, see section 19.3.7, LPC Channel 3 Address Register H, L
(LADR3H, LADR3L). In an LPC I/O read cycle, the data in the selected register is transferred to
the host.
The initial values of the ODR registers are undefined.
Section 19 LPC Interface (LPC)
Rev. 1.00 Mar. 12, 2008 Page 689 of 1178
REJ09B0403-0100
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