Advertisement
Section 6 Bus Controller (BSC)
Figure 6.1 Block Diagram of Bus Controller.............................................................................. 107
Figure 6.2 IOS Signal Output Timing ........................................................................................ 124
Figure 6.3 Access Sizes and Data Alignment Control (8-bit Access Space).............................. 125
Figure 6.4 Access Sizes and Data Alignment Control (16-bit Access Space) ............................ 126
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space ............................................................. 129
Figure 6.6 Bus Timing for 8-Bit, 3-State Access Space ............................................................. 130
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)........................... 131
Figure 6.8 Bus Timing for 16-Bit, 2-State Access Space (Odd Byte Access)............................ 132
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access) .................................. 133
Figure 6.10 Bus Timing for 16-Bit, 3-State Access Space (Even Byte Access)......................... 134
Figure 6.11 Bus Timing for 16-Bit, 3-State Access Space (Odd Byte Access) .......................... 135
Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access) ................................ 136
Figure 6.13 Glueless Extension Even Byte Access (ADMXE = 0)............................................ 137
Figure 6.14 Glueless Extension Odd Byte Access (ADMXE = 0) ............................................. 138
Figure 6.15 Glueless Extension Word Access (ADMXE = 0) ................................................... 139
Figure 6.16 Bus Timing for 8-Bit, 2-State Access Space ........................................................... 140
Figure 6.17 Bus Timing for 8-Bit, 2-State Access Space ........................................................... 141
Figure 6.18 Bus Timing for 8-Bit, 3-State Access Space ........................................................... 141
Figure 6.19 Bus Timing for 16-Bit, 2-State Access Space (1) (Even Byte Access) ................... 142
Figure 6.20 Bus Timing for 16-Bit, 2-State Access Space (2) (Even Byte Access) ................... 143
Figure 6.21 Bus Timing for 16-Bit, 2-State Access Space (3) (Odd Byte Access) .................... 143
Figure 6.22 Bus Timing for 16-Bit, 2-State Access Space (4) (Odd Byte Access) .................... 144
Figure 6.23 Bus Timing for 16-Bit, 2-State Access Space (5) (Word Access)........................... 145
Figure 6.24 Bus Timing for 16-Bit, 2-State Access Space (6) (Word Access)........................... 145
Figure 6.25 Bus Timing for 16-Bit, 3-State Access Space (1) (Even Byte Access) ................... 146
Figure 6.26 Bus Timing for 16-Bit, 3-State Access Space (2) (Odd Byte Access) .................... 147
Figure 6.27 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access)........................... 147
Figure 6.28 Example of Wait State Insertion Timing (Pin Wait Mode) ..................................... 149
Figure 6.29 Example of Wait State Insertion Timing................................................................. 151
Figure 6.30 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 1).................... 152
Figure 6.31 Access Timing Example in Burst ROM Space (AST = BRSTS1 = 0).................... 153
Figure 6.32 Examples of Idle Cycle Operation .......................................................................... 154
Section 7 Data Transfer Controller (DTC)
Figure 7.1 Block Diagram of DTC ............................................................................................. 160
Figure 7.2 Block Diagram of DTC Activation Source Control .................................................. 172
Figure 7.3 DTC Register Information Location in Address Space............................................. 173
Figure 7.4 DTC Operation Flowchart......................................................................................... 175
Figure 7.5 Memory Mapping in Normal Mode .......................................................................... 176
Figure 7.6 Memory Mapping in Repeat Mode ........................................................................... 177
Rev. 1.00 Mar. 12, 2008 Page xxx of xIviii
Advertisement
